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FPGA-Based Data Compression Drives Brain Imaging Performance Gains






To help broaden the use of single-photon avalanche diode (SPAD) cameras for multispeckle diffuse correlation spectroscopy (DCS), researchers at the University of Edinburgh developed a data compression scheme for a large-pixel-count SPAD camera using a field-programmable gate array (FPGA).

The camera system’s large sensor array enabled a substantial signal-to-noise ratio (SNR) gain over a single-pixel system: The researchers demonstrated an SNR gain of 110, with respect to single-pixel multispeckle DCS, using half of the 192 × 128 SPAD array. The pixel active fill factor was 13% — an order-of-magnitude-larger pixel count than in prior works, according to the team.

FPGA compression for large-array multispeckle DCS could democratize the use of SPAD cameras in the biomedical research community, the researchers believe, extending the benefits of multispeckle DCS across many areas of biomedical research.

DCS quantifies cerebral blood flow — an important indicator of brain health — by measuring the autocorrection function of diffused light introduced through the scalp. The light scatters through the deep tissue and returns a speckle pattern at the detector. The pattern fluctuates in intensity in response to the movement of the tissue and the blood circulating within it.

SPAD cameras have made it possible to capture many independent speckles at the same time, leading to multispeckle DCS instruments with high sensitivity. However, multispeckle DCS systems are hampered by the small number of pixels in a SPAD array and by a lack of camera-embedded processing capabilities. The extremely high data rates of SPAD cameras, which exceed the maximum data transfer rates of commonly used communication protocols, require large computing resources and limit the scalability of SPAD cameras to the higher pixel resolutions.

To enable practical use of SPAD cameras for multispeckle DCS, the researchers, led by professor Robert K. Henderson, connected a SPAD sensor array composed of 192 × 128 pixels to a commercial FPGA. They embedded an autocorrelation algorithm in the FPGA to make data compression scalable to large SPAD arrays. The algorithm can perform most of the calculations needed for DCS, and the system demonstrated the ability to calculate 12,288 autocorrelations in real time from the SPAD array output.

Shifting the computational burden from a host computing system to the hardware directly connected to the SPAD sensors alleviated the need for high-powered computing resources and extremely fast data transfer rates. The researchers ran the multispeckle DCS measurements in real time using a standard PC.

“Our proposed system achieved a significant gain in the signal-to-noise ratio, which is 110 times higher than that possible on a single-speckle DCS implementation and 3× higher than other state-of-the-art multispeckle DCS systems,” Henderson said.

Although the focus of the work is on FPGA-embedded processing for multispeckle DCS, the system can also operate in multispeckle time-domain DCS with a precision of 33-ps time-of-flight resolution, the researchers said.

In the future, the FPGA-based design for data compression could enable SPAD arrays for multispeckle DCS that provide high pixel resolution without requiring specialized, high-performance computing to calculate autocorrelators for real-time measurements.


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